#HDL_LIB comes from the top makefile
#LIB_F gets added to by each lib 
#everything else is local
SEG7_LIB := seg7
SEG7_FILES := \
	$(HDL_LIB)/$(SEG7_LIB)/seg7Scanner.vhd \
	$(HDL_LIB)/$(SEG7_LIB)/decodeSeg7.vhd
LIB_F += $(SEG7_LIB).tmpprj

$(SEG7_LIB).tmpprj: $(SEG7_FILES)
#for i in $(SEG7_FILES); do if [ "$${i##*.}" = "vhd" ]; then echo "vhdl $$SEG7_LIB \"$$i\""; elif [ "$${i##*.}" = "v" ]; then echo "verilog $$SEG7_LIB \"$$i\""; fi; done >> $(TOP_LEVEL).prj
	for src in $(SEG7_FILES); do echo "vhdl" $(SEG7_LIB)" \"$$src\"" >> $(SEG7_LIB).tmpprj; done
